1. Field of the Invention
The present invention relates to a memory device, a display control driver with the same, and a display apparatus using the display control driver.
2. Description of the Related Art
FIG. 1 is a block diagram showing a conventional liquid crystal display apparatus (LCD). As shown in FIG. 1, an LCD 101 includes a CPU 2 for generating a display data, an LCD control driver 103, and an LCD panel 4 for displaying the display data. The LCD control driver 103 stores the display data generated by the CPU 2 for a one screen and then outputs the held display data for one horizontal line to the LCD panel 4 at a time. The LCD control driver 103 is composed of a display RAM (Random Access Memory) 105 for storing the display data, a control circuit 106 for controlling the display RAM 105, and a latch section 107 for latching the display data for one horizontal line outputted from the display RAM 105, and then outputting to the LCD panel 4 at a time.
In addition to a write operation by the CPU 2 (hereafter, to be referred to as a CPU write operation) and a read operation by the CPU 2 (hereafter, to be referred to as a CPU read operation), a read operation from the display RAM 105 to the LCD panel 4 is required (hereafter, to be referred to as an LCD read operation). The LCD read operation is asynchronous with the CPU write/read operation. The CPU read operation is carried out for verification of whether or not the display data is surely written into the display RAM 105, a test in case of failure occurrence, and an operation to the display data. At this time, in order to avoid conflict between the CPU write/read operation and the LCD read operation, it could be considered to use a RAM having one write port and two read ports. However, such a RAM is large in area and high in cost. For these reasons, usually, one port RAM is used as the display RAM, and an arbitration control is carried out based on a time division method, as described in International Publication WO 00/03381.
FIG. 2 is a circuit diagram showing the conventional LCD control driver having the display RAM with one port. FIGS. 3A to 3C are timing charts showing the operation of the LCD control driver. FIGS. 4A-1 to 4A-6 are diagrams showing the operation of this LCD control driver 103 for each cell. FIGS. 4B-1 and 4B-2 are timing charts showing the operation of the LCD control driver 103. As shown in FIG. 2, memory elements 8 are arranged in a matrix in the display RAM 105. The memory elements 8 of a predetermined number arranged in one row as an X-direction constitute one cell 9 for storing the display data for one pixel. The number of memory elements 8 constituting one cell 9 is 18 in this example, and the memory elements 8 store 18 bits of the data. This means that each pixel of the display data is displayed in three colors and has gradation levels of 26 per color. Addresses (XADDi, YADDj) are allocated to the cells 9 as shown in FIG. 2. It should be noted that the X-direction shown in FIG. 2 corresponds to the horizontal direction of the LCD panel 4, and the Y-direction corresponds to the vertical direction of the LCD panel 4.
Also, one word line 111 is provided for each of rows of the memory elements 8 arrayed in the X-direction. Also, one data line 12 and one bit line 13 are provided for each of columns of the memory elements 8 arrayed in the Y-direction. Consequently, each of the memory elements 8 is connected to the word line 111, the data line 12 and the bit line 13. Also, the latch section 107 contains a plurality of latches 10, each of which is provided for one column of the memory elements 8. Thus, the number of the latches 10 is equal to the number of the columns of the memory elements 8. Each of the latches 10 is connected to the memory elements 8 of one column through data lines 12, and all of the latches 10 are connected to a common wiring 114.
The operation of the conventional LCD control driver 103 will be described below. As described later, a request of the LCD read operation is generated asynchronously with the CPU write/read operation. However, the one port RAM can not carry out the CPU write/read operation and the LCD read operation at a same time. Thus, the time division control is carried out. As shown in FIGS. 3A to 3C, it is supposed that the LCD read request is generated at a time T101. The LCD read operation is started in response to the LCD read request. However, if the CPU write operation is started at a time T102 during the LCD read operation, the LCD read operation is stopped. After the CPU write operation is ended at a time T103, the LCD read operation is restarted. It should be noted that the CPU write operation is carried out in a relatively large power supplied from the control circuit 106, and the LCD read operation is carried out in a small current accumulated in the memory elements 8. For this reason, the LCD read operation needs an access time longer than that of the CPU write operation. For example, the LCD read operation needs the access time equal to three times of the access time of the CPU write operation.
The operation of this conventional LCD control driver 103 will be described below in detail with reference to FIGS. 4A-1 to 4A-6 and 4B-1 and 4B-2. In order to simplify the description, FIGS. 4A-1 to 4A-6 and 4B-1 and 4B-2 show only the cells arrayed in a matrix of 3 rows×5 columns. In FIGS. 4A-1 to 4A-6, the cell noted as [CPU] indicates that the cell is in the CPU write operation, and the cell noted as [LCD] indicates that the cell is in the LCD read operation. As shown in FIGS. 4A-1 to 4A-6, and 4B-1 and 4B-2, at a time T111, the CPU write operation is carried out on the cell specified by an address (X=0, Y=0) (hereafter, to be referred to as the cell (X=0, Y=0)). At this time, the CPU write/read operation and the LCD read operation are not carried out on the other cells.
Next, after the end of the CPU write operation to the cell (X=0, Y=0), the LCD read operation is carried out on a row of cells specified by the address (Y=0) during a period of a time T112 to a time T114. As mentioned above, the LCD read operation requires the access time equal to three times of the access time of the CPU write operation. Thus, the LCD read operation is not completed only at the time T112, and the LCD read operation is completed at the time T114. In FIG. 4A-4, this is indicated by an index t noted within each cell. That is, it is supposed that in association with the time elapse of T112→T113→T114 in the LCD read operation, the index t is increased one by one, as 1→2→3, and at the time of t=3, the LCD read operation is completed. A cell noted as [OK] indicates the cell in which the LCD read operation is completed. It should be noted that if the LCD read operation is stopped prior to t=3, a next LCD read operation is again counted from t=1. During a period of the time T112 to the time T114, the CPU 2 can not carry out the CPU write operation to the other cells. Then, a wait time is generated.
Next, at a time T115, the CPU write operation is carried out on a cell (X=1, Y=0). In a period of a time T116 to a time T118 after the time T115, neither the CPU write operation nor the LCD is carried out. At this time, the wait time is generated in the CPU 2. Then, at a time T119, the CPU write operation is carried out on a cell (X=2, Y=0). After that, the similar operation is carried out. At this time, the operation cycle of the CPU 2 is the four unit times from the times T111 to T114. Thus, the 20 unit times are required to carry out the CPU write operation to the cell rows specified by the addresses (X=0 to 4, Y=0).
However, this conventional example contains the following problems. As mentioned above, in the LCD control driver 103, the CPU write operation is generated at a constant cycle and has a priority over the LCD read operation so as not to impose a burden on the CPU 2. However, the LCD read operation is an operation for writing the display data to the LCD panel 4, and it is necessary to always carry out within a certain period. For this reason, in order to reserve a time period during which the LCD read operation is carried out, the operation cycle of the CPU write operation needs to be sufficiently low. Consequently, the wait time is generated in the CPU 2. During the wait time, however, the CPU 2 can not carry out other processes and is in the wait state. As a result, the CPU 2 can not operate at an original operation speed. In this way, the operation speed of the CPU is inevitably made slower as the result of the usage of the one port RAM as the display RAM.
In recent years, the attainment of many functions, many gradations and a larger screen is demanded to the LCD installed in a portable terminal such as a mobile phone. For this reason, the scale of a display RAM built in the LCD is increased more and more. On the other hand, the higher performances such as the improvement of an access speed and the decrease in power consumption are demanded to the display RAM. In this case, from the viewpoint of the increase of the scale of the RAM, even the maintenance of the present performances becomes difficult. Thus, a technique is desired that can make the CPU operation speed higher while using the one port RAM as the display RAM.
For this purpose, a technique is proposed in which one memory is additionally installed in a LCD control driver, display data is written from a CPU to the memory, and then the CPU is released, as disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 6-324650) as a second conventional example. Thus, the load on the CPU can be reduced, thereby making the operation speed of the CPU faster. However, the above-mentioned second conventional example has the following problems. That is, the technique disclosed in the second conventional example needs to further install one memory in addition to the display RAM. Thus, the scale of the LCD control driver is made larger, and the cost is increased.